`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 16:16:12
// Design Name: 
// Module Name: wb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module wb(
    clk,rd_mem,data,data_mem,rd_wb,data_wb,op_rd_mem,addr_next_mem,data_fw_2
    );
    input clk;
    input [4:0] rd_mem;
    input [31:0] data,data_mem;
    input [1:0] op_rd_mem;
    input [31:0] addr_next_mem;
    output [4:0] rd_wb;
    output reg [31:0] data_wb;
    output [31:0] data_fw_2;

    assign rd_wb = rd_mem;
    assign data_fw_2 = data_wb;
    
    always @(*) begin
        case(op_rd_mem)
            2'b00 : data_wb = data;
            2'b01 : data_wb = data_mem;
            2'b10 : data_wb = addr_next_mem; 
            default : data_wb = 32'bx;
        endcase
    end
    
endmodule
